The fabrication process and experimental characterization techniques relevant to single-electron pumps based on silicon metal-oxide-semiconductor quantum dots are discussed.
As mass-produced silicon transistors have reached the nano-scale, their behavior and performances are increasingly affected, and often deteriorated, by quantum mechanical effects such as tunneling through single dopants, scattering via interface defects, and discrete trap charge states. However, progress in silicon technology has shown that these phenomena can be harnessed and exploited for a new class of quantum-based electronics. Among others, multi-layer-gated silicon metal-oxide-semiconductor (MOS) technology can be used to control single charge or spin confined in electrostatically-defined quantum dots (QD). These QD-based devices are an excellent platform for quantum computing applications and, recently, it has been demonstrated that they can also be used as single-electron pumps, which are accurate sources of quantized current for metrological purposes. Here, we discuss in detail the fabrication protocol for silicon MOS QDs which is relevant to both quantum computing and quantum metrology applications. Moreover, we describe characterization methods to test the integrity of the devices after fabrication. Finally, we give a brief description of the measurement set-up used for charge pumping experiments and show representative results of electric current quantization.
Silicon is the material of choice for most of the modern microelectronics. Its properties, combined with advanced lithographic techniques, have allowed the semiconductor industry to achieve very large-scale integration and deliver billions of transistors per chip. The metal-oxide-semiconductor (MOS) technology1 has been the key of this relentless technological progress2. In brief, it is based on a selectively doped Si substrate which is thermally oxidized to grow a high quality SiO2 gate oxide on which a metal gate electrode is deposited. Recently, it has been shown that the use of a stack of gate oxides could be beneficial3 . While present industry standards have reached minimum feature sizes for gate lengths below 20 nm, it is becoming increasingly evident that, at this level of miniaturization, detrimental quantum mechanical phenomena come into play that may complicate further downscaling4.
Remarkably, silicon is also an excellent host material to exploit the quantum properties of the electron charge and spin5. This has broadened its range of applicability to entirely new fields such as quantum computing6 and quantum electrical metrology7. Among other approaches5, the use of a multi-gate MOS technology8,9 has led to electrostatically-defined quantum dots (QD) whose occupancy can be controlled down to single-electron level10. Unlike the conventional MOS process where just one gate per transistor is needed1, these QDs are defined via a three-layer stack of Al/AlyOx gates which are used to selectively accumulate electrons at the Si/SiO2 interface, as well as provide lateral and vertical confinement11.
Although these devices had been originally developed for quantum computing applications, they have also recently shown promising performances as metrological tools12,13. In the field of quantum electrical metrology, a long-standing goal is the redefinition of the unit ampere in terms of the elementary charge (e) 14. In particular, the emphasis is on the realization of nano-scale charge pumps to clock the transfer of individual electrons timely and accurately. These devices generate macroscopic quantized electric currents, I=nef, where f is the frequency of an external driving oscillator and n is an integer. To date, the best performance has been achieved with a GaAs-based pump by yielding a current in excess of 150 pA with a relative uncertainty of 1.2 parts per million15. Recently, silicon MOS QDs have also stood out for the implementation of highly accurate single-electron pumps thanks to the capability of finely tuning the charge confinement13.
Here, we discuss the protocol used for the fabrication of silicon MOS QDs. Furthermore, the cryogenic set-up used to test the integrity of the devices after fabrication and the one to perform charge pumping experiments are described. Finally, representative measurements of quantized electric current are reported.
Protokollen rapporteret i dette papir beskriver teknikker til at fremstille silicium MOS QDs, samt de eksperimentelle procedurer til at teste deres funktionelle integritet og drive dem som enkelt-elektron pumper. Bemærkelsesværdigt, ved at skræddersy porten design, den samme fremstillingsproces kan anvendes til at fremstille apparater, for quantum bit udlæsning og kontrol 17 samt ladningspumpeorganerne 12,13. Vi bemærker, at mange af de procesparametre citeret i denne artikel kan variere afhængigt af fabrikation værktøjer (kalibrering, mærke eller model), samt af typen af silicium substrat (tykkelse og baggrund doping tæthed). Mængder såsom dosis litografi eksponering eller udviklingstid, ætsning eller oxidering varighed, skal omhyggeligt kalibreret og testet for at sikre en pålidelig udbytte. Desuden er det afgørende at undgå krydskontaminering som følge af brugen af de samme fabrikation værktøjer til forskellige processer. Til dette formål et antal crtiske trin udføres med udstyr udelukkende til silicium forarbejdning, såsom metal fordampere, ilt ovne og HF bade.
Mere generelt er silicium trække en stigende interesse som det foretrukne materiale til at realisere charge pumper 18-20. Dette skyldes til dels den attraktive perspektiv implementere en ny kvante-baserede elektrisk strøm standard ved hjælp af en industri-kompatibel silicium proces. Dette vil have gavn af veletablerede og pålidelige integration teknikker til skalerbarhed, parallelisering og kørsel overhead. Vigtigere er det, en fuld supplerende MOS (CMOS) teknologi, fri for traditionel metal som porten materiale, har vist stærkt reducerede afgift udsving baggrund i single-elektron enheder 21. Sådanne udsving kan være skadelige i at opnå metrologiske nøjagtigheder.
Protokollen diskuteret her er begrænset til realiseringen af MOS nano-enheder med metal porte. Derfor, for at achieve fuld industriel kompatibilitet og reducere charge udsving, ville det være nødvendigt at modificere gate aflejringsteknikker og bruger højt doteret polykrystallinsk silicium som porten materiale.
Afslutningsvis har MOS QD pumperne diskuteret her for nylig kombineret det teknologisk fordel af silicium med meget gode resultater i form af præcise nuværende generation 13. Dette skyldes den høje fleksibilitet af design og fabrikation proces, som tillader en at stable flere gate lag fører til en kompakt og alsidigt system. Det resulterende fine justerbarhed af den elektrostatiske indespærring af dot sammen med potentiale til at reducere baggrund charge udsving sætter scenen for at overvinde de vigtigste udfordringer observeret i andre halvleder pumper 22,23.
The authors have nothing to disclose.
Vi takker KY Tan, P. See og GC Tettamanzi for nyttige diskussioner. Vi anerkender økonomisk støtte fra forskningsrådet australske (Grant No. DP120104710), Finlands Akademi (Grant No. 251.748, 135.794, 272.806) og støtte fra Australian National Fabrication faciliteten for enhedens opspind. AR anerkender økonomisk støtte fra University of New South Wales Early Career Forsker Grant ordningen. Tilvejebringelse af faciliteter og teknisk support ved Aalto University på Micronova nanofabrikation Centre er også anerkendt.
Silicon wafers | TOPSIL | 4 inch | |
Electron-beam lithography machine | Raith gmbh | Raith 150two | |
E-beam resist | MicroChem gmbh | PMMA | |
Photoresist | MicroChem gmbh | nLOF2020 | |
Mask aligner | Quintel | Q6000 | |
Photoresist developer | MicroChem gmbh | AZ826MIF |